An H100 operation costs about 100 million Landauer limits

Key takeaways

• Erasing one bit must release at least kT ln 2 of heat (Landauer, 1961): 2.87 × 10^-21 J at 300 K.
• Experiments from 2012 to 2016 measured the cost near the bound of 0.693 kT. The 2016 nanomagnet test gave 1.45 kT, with an uncertainty of 0.35 kT.
• An H100 SXM at its 700 W rating and 1,979 dense FP8 teraFLOPS spends at most 3.54 × 10^-13 J per operation, about 1.03 × 10⁸ times kT ln 2 at 358.15 K (our arithmetic, an order of magnitude only).
• In a 2014 reference for a 45 nm process, a 32-bit add costs 0.1 pJ and a 64-bit DRAM access costs 1.3 to 2.6 nJ.
• The Landauer limit is no floor for switching a transistor. The company selling reversible chips shows no measured result on its own pages.

This is part 2 of our series on the physics of the data centre. Part 1 of the series explains why data in optical fibre is slower than light.

Rest a laptop on your knees through an hour of video calls, and your legs feel it. Hold a phone through a long video and the back of it turns warm. That heat is electrical energy the chip took from the wall or the battery, used and threw away.

How little heat could a computer give off? And how far is a modern AI chip from that minimum? Physics gives a firm answer to the first question for one operation: erasing a bit of information. For the second, take one H100 at its peak rate: it spends about 100 million times that bit-erasure energy on each operation. The ratio is a scale, not a like-for-like comparison, and this article shows where it comes from.

Two guesses are natural. The first says chips must already sit near the physical minimum, after decades of improvement. The second says the Landauer limit is the price of every transistor switch. The numbers below test both.

What Landauer showed in 1961

A bit is a memory with two possible states, 0 and 1. Resetting it to a known state, say 0, destroys the old value. Two different pasts now lead to the same present. Landauer’s 1961 paper in the IBM Journal of Research and Development starts from that point.

The merge has a price. The bit could be in either of two states before the reset and is in one afterwards. Landauer calculated that its entropy, a measure of how many arrangements it can take, falls by k ln 2 = 0.693 k, where k is the Boltzmann constant. That entropy has to go to the surroundings as heat. At temperature T the heat is at least kT ln 2 for each erased bit.

Landauer added a caveat. His method of reasoning, he wrote, “gives no guarantee that this minimum is in fact achievable.” Only logically irreversible steps pay, meaning steps whose input you cannot rebuild from the output. Erasing a bit is the clearest case.

A worked calculation: the floor and an H100

The Boltzmann constant is k_B = 1.380649 × 10^-23 joules per kelvin, which NIST lists as exact. Kelvin is the temperature scale that starts at absolute zero. We use 300 K as a mild room and 358.15 K (85 °C) as a hot chip. The second is our illustrative choice, not an NVIDIA specification. We found no primary NVIDIA figure for operating temperature.

Quantity	Calculation	Result
kT at 300 K	1.380649 × 10-23 J/K × 300 K	4.14195 × 10-21 J
kT ln 2 at 300 K	4.14195 × 10-21 J × 0.693147	2.871 × 10-21 J = 2.87 zJ = 17.9 meV
kT at 358.15 K	1.380649 × 10-23 J/K × 358.15 K	4.94479 × 10-21 J
kT ln 2 at 358.15 K	4.94479 × 10-21 J × 0.693147	3.427 × 10-21 J = 3.43 zJ = 21.4 meV
H100 SXM energy per dense FP8 operation	700 W / (1.979 × 1015 operations per second)	3.54 × 10-13 J = 0.354 pJ
Ratio to kT ln 2 at 358.15 K	3.54 × 10-13 J / 3.427 × 10-21 J	1.03 × 108
Ratio to kT ln 2 at 300 K	3.54 × 10-13 J / 2.871 × 10-21 J	1.23 × 108

A zJ is a zeptojoule, 1 × 10^-21 J. A meV is a thousandth of an electronvolt, the energy of one electron moved across one volt (1 eV = 1.602176634 × 10^-19 J).

Now the chip. The NVIDIA H100 page lists the SXM version at up to 700 W (configurable) and 3,958 teraFLOPS of FP8 throughput. A teraFLOP is 1 × 10¹² floating-point operations per second. FP8 means numbers stored in 8 bits. The page marks 3,958 as a figure with sparsity, a chip feature that raises the quoted rate. A preliminary table in NVIDIA’s Hopper architecture blog lists dense and sparse rates in pairs, with the sparse rate double. We halve the page figure to get 1,979 teraFLOPS dense. NVIDIA does not print that number, so it is our derivation. The page gives no energy per operation, so we divide power by throughput.

The result is 3.54 × 10^-13 J per operation, or 0.354 pJ (a picojoule is 1 × 10^-12 J). Against the hot-chip floor of 3.427 × 10^-21 J, the ratio is 1.03 × 10⁸. That is about eight orders of magnitude.

Treat the ratio as a scale and as an upper bound at peak rate. The 700 W is a ceiling for the board, not a measured draw. A chip below its rating at peak speed would cost less per operation, and an idle one would cost more per useful operation. The figure covers the accelerator board only. Most important, a FLOP is not a bit erasure. One multiply-accumulate (a multiplication added to a running total) involves many gate transitions and many erasures, and some bits are never erased.

Three experiments that measured the floor

Landauer’s argument is theory. Three experiments tested it. Each reports its result in units of kT, so you can set it against the bound of 0.693 kT.

In 2012 Bérut and colleagues (Nature 483:187) erased one bit stored by a single silica bead, micrometre-sized, in water. Laser light held the bead in a trap with two dips in energy, left and right, that stand for 0 and 1. To erase, the team lowered the barrier between the dips, tilted the trap so the bead moved to one side, and raised the barrier. The mean heat levels off at the Landauer bound as the cycles grow long.

The numbers come from a companion paper (Bérut, Petrosyan and Ciliberto, arXiv:1503.06537), not from the Nature paper. The tilt lasted a time tau, and the longest example run had tau = 40 s. The mean heat fits kT ln 2 + B/tau, with B = 8.15 kT s. A fit that leaves the first term free gives 0.72 kT; the individual data points carry error bars of about 0.15 kT. Some single runs gave off less heat than the bound, which makes it a bound on the mean.

In 2014 Jun, Gavrilov and Bechhoefer (Phys. Rev. Lett. 113:190601) trapped a 200 nm fluorescent particle with a feedback trap. Electrodes applied a computer-controlled force, updated every 10 ms, to imitate a landscape with a barrier 13 kT high. The work to erase, extrapolated to infinitely slow cycles, is 0.71 kT with an uncertainty of 0.03 kT. A control with no erasure gave 0.05 kT. The 0.71 is an extrapolation and not a direct measurement.

In 2016 Hong and colleagues (Science Advances 2:e1501492) reset a bit stored in the magnetic direction of an elliptical nanomagnet, cut from a 10 nm Permalloy film. The energy came from precise magnetometry, not a heat measurement. At 300 K the average of five trials was 6.09 zJ with an uncertainty of 1.43 zJ, which is 1.45 kT with an uncertainty of 0.35 kT. The paper gives the limit as 2.8 zJ, so our division puts the measurement at 2.2 times the bound. The authors call it consistent with the limit within two standard deviations.

In both bead experiments the cost approaches the bound only as cycles lengthen. At finite speed it is higher.

A ladder of energies, from the floor to a prompt

The chart puts nine energies on one log scale. Each rung is energy per the unit in its label (a bit, an operation or a prompt), so read the rungs as a scale only.

The ladder answers the first guess, that chips already sit near the floor. They do not. A 32-bit integer add at 45 nm, which costs 0.1 pJ, is 2.9 × 10⁷ times kT ln 2 at 358.15 K. The H100 rungs sit at 5.2 × 10⁷ for the sparse rate and 1.03 × 10⁸ for the dense rate. A DRAM access reaches 5.9 × 10⁹ per bit or more.

Where the energy really goes

Arithmetic is the cheap part. Horowitz set out the standard comparison in his 2014 ISSCC talk, “Computing’s energy problem (and what we can do about it)” (DOI 10.1109/ISSCC.2014.6757323). His figure 1.1.9 lists rough energy costs at 45 nm and 0.9 V. That is a 2014 reference for an older process, not an H100, so use it for proportions.

Operation (45 nm, 0.9 V)	Energy
32-bit integer add	0.1 pJ
32-bit floating-point multiply	3.7 pJ
64-bit read, 8 KB cache	10 pJ
64-bit read, DRAM	1.3 to 2.6 nJ

A DRAM access costs 13,000 to 26,000 times a 32-bit add (our division of 1.3 or 2.6 nJ by 0.1 pJ). Per bit, that is 20.3 to 40.6 pJ. A simple in-order processor spends about 70 pJ per instruction, and the add itself is a thin slice of it.

Memory stacked beside a GPU is cheaper per bit. O’Connor and colleagues at NVIDIA modelled HBM2, a stacked memory built for GPUs, at about 3.97 pJ per bit (MICRO-50, 2017). That is still 1.2 × 10⁹ times kT ln 2 at 358.15 K. We found no vendor figure for newer generations, so we quote none.

How fast the gap has been closing

Chips did get better, and the record is long. Koomey and colleagues found in 2011 that computations per kilowatt-hour doubled every 1.57 years from 1946 to 2009. In 2015 Koomey and Naffziger wrote in IEEE Spectrum that the trend began to end around 2000. Since then, they said, peak-output efficiency takes about 2.7 years to double.

The next lines are arithmetic for illustration. The ratio of 1.03 × 10⁸ equals 26.6 doublings (the base 2 logarithm). At 1.57 years each, that is 42 years. At 2.7 years each, it is 72 years. It sets energy per FLOP against a bit-erasure bound, so it shows scale only. Nothing guarantees that either rate holds.

Reversible computing avoids the erasure

The second guess says kT is a floor for every transistor switch. Theis and Wong (Computing in Science & Engineering, 2017) write that some people have read it that way, and that Landauer knew it was not so. The floor applies to erasing information. Even in the smallest transistors, the stored energy that marks a digital state is orders of magnitude above kT. They attribute this to design needs such as telling a digital state reliably from thermal noise, and to dumping the stored energy at each switch.

Bennett showed in 1973 (DOI 10.1147/rd.176.0525) that a computer can be logically reversible at every step. It keeps every intermediate result, prints the answer, then retraces its steps backward to dispose of the intermediates. No bit is erased, so the floor does not apply. The price is memory and time.

Frank of Sandia makes the case for reversible computing in a 2018 review. He says adiabatic CMOS, which moves charge gradually between circuit nodes, is arguably too slow for near-term gains. Frank later joined Vaire, a company building reversible chips, so read his case as advocacy. Theis and Wong noted that no commercially viable energy-conserving computing system had emerged since the 1990s.

Vaire’s own website (vaire.co) and its linked whitepaper, which we opened on 11 October 2026, state goals and define an energy recovery factor. They show no measured result. Its About page says all computation will be reversible in 15 years, which is the company’s forecast. Press reports on its test chip describe different things. IEEE Spectrum reported in 2025 a prototype capable of recovering 50% of the energy used in its resonator circuit. Science News reported on 23 September 2025 that a test chip, tested in August, drew around 30 percent less energy than a regular chip. MIT Technology Review reported on 8 September 2026 a resonator that recovered more energy than it lost. We could not reconcile these reports from a primary page, so we do not combine them.

From one bit to one prompt

Move from one bit to one request. Google’s August 2025 paper by Elsworth and colleagues (arXiv:2508.15734) measured the median Gemini Apps text prompt at 0.24 Wh, which is 864 J (at 3,600 J per Wh). Active AI accelerators account for 0.14 Wh (504 J, 58%). The host processor and memory use 0.06 Wh (25%), idle machines 0.02 Wh (10%), and data-centre overhead counted through power usage effectiveness (PUE) 0.02 Wh (8%).

This is Google’s own measurement of its own service, a fleet average for text prompts in May 2025, in a preprint. It does not describe other vendors or other requests. Accelerators account for 58% of a prompt’s energy. Hosts, idle machines and the building account for the rest.

Try it with your own workload

Open the AI energy calculator to see what your own AI workload uses. Then open the accelerator power dataset to find the power rating of the chip you run on.

You can repeat the worked example for that chip. Take its power rating and divide it by the peak operations per second on its datasheet. Check first whether the datasheet rate is dense or sparse, because the H100 page prints only sparse figures. Divide the result by kT ln 2 at your chosen temperature: 1.380649 × 10^-23 J/K times that temperature in kelvin times 0.693147.

For the median Gemini prompt, 864 J divided by 3.427 × 10^-21 J gives 2.5 × 10²³. That compares a whole request with a single bit, so read it as a scale only.

Sources

1. Landauer, Irreversibility and Heat Generation in the Computing Process, IBM J. Res. Dev. 5(3):183-191, 1961, DOI 10.1147/rd.53.0183
2. Bennett, Logical Reversibility of Computation, IBM J. Res. Dev. 17(6):525-532, 1973, DOI 10.1147/rd.176.0525
3. Bennett, Notes on Landauer’s principle, reversible computation, and Maxwell’s Demon, Stud. Hist. Phil. Mod. Phys. 34(3):501-510, 2003
4. Bérut et al., Nature 483:187-189, 2012, DOI 10.1038/nature10872
5. Bérut, Petrosyan and Ciliberto, companion paper, J. Stat. Mech. 2015, arXiv:1503.06537
6. Jun, Gavrilov and Bechhoefer, Phys. Rev. Lett. 113:190601, 2014, DOI 10.1103/PhysRevLett.113.190601
7. Hong, Lambson, Dhuey and Bokor, Science Advances 2(3):e1501492, 2016, DOI 10.1126/sciadv.1501492
8. NIST, CODATA value of the Boltzmann constant
9. NVIDIA, H100 GPU product page (specification table)
10. NVIDIA developer blog, Hopper architecture in depth
11. Horowitz, Computing’s energy problem (and what we can do about it), 2014 IEEE ISSCC Digest of Technical Papers, pp. 10-14, DOI 10.1109/ISSCC.2014.6757323 (a copy of the digest page is at pages.cs.wisc.edu)
12. O’Connor, Chatterjee, Lee, Wilson, Agrawal, Keckler and Dally, Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems, MICRO-50, 2017
13. Koomey, Berard, Sanchez and Wong, Implications of Historical Trends in the Electrical Efficiency of Computing, IEEE Annals of the History of Computing 33(3):46-54, 2011
14. Koomey and Naffziger, Moore’s Law Might Be Slowing Down, But Not Energy Efficiency, IEEE Spectrum, 31 March 2015
15. Theis and Wong, Computing in Science & Engineering 19(2):41-50, March/April 2017
16. Frank, Back to the Future: The Case for Reversible Computing, arXiv:1803.02789, 2018
17. Vaire Computing (home, About and whitepapers pages, opened 11 October 2026)
18. Genkina, Reversible Computing Escapes the Lab in 2025, IEEE Spectrum, 2 January 2025 (editor’s update 22 May 2025)
19. MIT Technology Review, article on Vaire’s chip, 8 September 2026
20. Science News, This experimental computer chip reuses energy, 23 September 2025
21. Elsworth et al. (Google), Measuring the environmental impact of delivering AI at Google Scale, arXiv:2508.15734, August 2025

@online{scienceshot-landauer-limit-ai-chips-2026,
  author       = {Turner, Alex},
  title        = {{An H100 operation costs about 100 million Landauer limits}},
  organization = {ScienceShot},
  date         = {2026-10-27},
  year         = {2026},
  url          = {https://scienceshot.com/post/landauer-limit-ai-chips}
}